1. Technical Field of the Invention
The present invention relates to a layout structure of multiplexer cells, and in particular, it relates to a multiplexer cell layout structure having primitive cells wherein cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows.
2. Description of the Related Art
In recent years, semiconductor integrated circuits (hereinafter, referred to as LSIs) designed as ASICs are well known. Of these, LSIs having a layout structure of primitive cells wherein a cell array composed of P-channel transistors and N-channel transistors is arranged in a single horizontal row are known.
Such LSIs are disclosed in Japanese Published Unexamined Patent Application No. 2002-141477 and Japanese Published Unexamined Patent Application No. H05-251671, for example.
In general, it is widely known that small-scale layouts block drawn at a transistor level utilized in layout design of one chip are called primitive cells (or primitive blocks).
Primitive cells have logical functions such as an inverter, a buffer, a NAND, a NOR, a multiplexer, and a flip-flop. And, the inverter is referred to as an inverter cell, the buffer is referred to as a buffer cell, the NAND is referred to as a NAND cell, the NOR is referred to as a NOR, the multiplexer is referred to as a multiplexer cell, and the flip-flop is referred to as a flip-flop cell.
In addition, a primitive cell has a layout form wherein a P-channel transistor region and an N-channel transistor region are adjacently arranged up and down (or right and left) and a plurality of P-channel transistors and a plurality of N-channel transistors are lined up in the lateral direction (or the longitudinal direction). In a layout structure of multiplexer primitive cells as well, the primitive cell is composed of a cell array wherein P-channel transistors and N-channel transistors are adjacent and lined up in a row.
FIG. 1 is a circuit diagram for a layout of a conventional layout structure using a 4-input multiplexer-inverter circuit.
A conventional multiplexer circuit layout structure has primitive cells as described above. And, the layout structure has a cell layout structure wherein, on multiplexer circuits (401, 402, 403, and 404) having a plurality of transfer gate outputs or inverter outputs, or both thereof, transfer gate transistors (409-1, 409-2, 409-3, and 409-4) are arranged in a single cell array 406, and an output terminal (N01) of the arranged transistors is connected within the single cell array 406 by use of a polysilicon layer, 1-layer metal wiring, and 2-layer metal wiring.
Furthermore, the conventional multiplexer circuit layout structure employs a cell layout structure wherein a multiplexer decoding circuit 405 is arranged on the right side of the output terminal (N01), internal wiring of the decode circuit is connected within the single cell array 406 by use of a polysilicon layer, 1-layer metal wiring, and 2-layer metal wiring, and signal wiring to control the transistor gate circuit transistor outputs is connected within the single cell array 406 by use of a polysilicon layer, 1-layer metal wiring, and 2-layer metal wiring right and left.
In FIG. 2, wiring tracks 701 of 2-layer metal wiring of the prior-art 4-input multiplexer-inverter as shown in FIG. 1 are shown. In the drawing, “x” shows wiring tracks of 2-layer metal wiring 702 used by cells, which means that the tracks cannot be used as wiring tracks of 2-layer metal wiring of one chip.
In addition, as another prior art, a circuit diagram of a 2-staged transfer gate-type 4-input multiplexer is shown in FIG. 3. In a 2-staged transfer gate-type 4-input multiplexer 900, first-stage transfer gates are composed of a first-stage transfer gate 909-1 to receive a signal from an input terminal H01, a first-stage transfer gate 909-2 to receive a signal from an input terminal H02, a first-stage transfer gate 909-3 to receive a signal from an input terminal H03, and a first-stage transfer gate 909-4 to receive a signal from an input terminal H04.
Furthermore, in the 2-staged transfer gate-type 4-input multiplexer 900, second-stage transfer gates are composed of a second-stage transfer gate 909-5 to receive an output from the first-stage transfer gate 909-1 and an output from the transfer gate 909-2 and a second-stage transfer gate 909-6 to receive an output from the first-stage transfer gate 909-3 and an output from the transfer gate 909-4.
Moreover, an output terminal (N01) to receive an output from the second-stage transfer gate 909-5 and an output from the second-stage transfer gate 909-6 is provided.
However, if transistors of a prior-art multiplexer-inverter circuit are arranged in a single row in the lateral direction, a transfer gate circuit part (401, 402, 403, and 404) inside the cells requires, as shown in FIG. 1, a total of five lateral wiring tracks, four for control signals and one for outputting, for wiring inside the cells, and a 2-4 decoder circuit part requires eight lateral wiring tracks for wiring inside the cells.
On the other hand, since lateral wiring tracks of a polysilicon layer and 1-layer metal wiring of a prior-art cell layout structure are reduced by terminals and power supply wiring, etc., usually only approximately four exist in total. Accordingly, for the rest of the wiring, 2-layer metal wiring whose principal axis is in the longitudinal direction is wired in the lateral direction.
This lateral 2-layer metal wiring consequently intersects with the vertical axis, which is a principal axis of a 2-layer metal wiring channel of one chip, and approximately 30 wiring tracks 702 of the 2-layer metal wiring are used. Therefore, 2-layer metal wiring tracks of one chip are greatly reduced, and wireability of one chip greatly lowers.